A new manufacturing technique could keep Moore's Law alive by stacking silicon circuits in multiple layers, bypassing the limits of traditional chip miniaturization. The approach, detailed by researchers, uses ultra-thin silicon membranes and low-temperature processes to create true 3D chips.
For years, the semiconductor industry has struggled to pack more transistors onto flat surfaces as physical limits approach. This stacking method offers a path forward without requiring entirely new materials or radical architecture changes.
The process solves a key obstacle that prevented reliable 3D chip production: heat buildup and material stress during fabrication. By operating at lower temperatures, the technique allows delicate layers to bond without damage.
If scaled commercially, this could extend the lifespan of current design paradigms and buy time for next-generation technologies. Chipmakers may adapt existing fabs with modifications rather than building entirely new facilities.
The researchers acknowledged that cost and yield remain significant hurdles before the method reaches mass production. Independent experts have not yet verified the claims in a peer-reviewed setting.